Instruction-Set Extension and Implementation of a RISC-V Processor for a Driver Fatigue Detection System

Project Partners

Istanbul Technical University
Urmia University
TÜBİTAK

Project Team

Project Summary

Embedded systems are designed to meet application-specific performance requirements, including speed, accuracy, reliability, and cost efficiency. By definition, an embedded system consists of application-specific hardware and software components. However, as the complexity of the target system increases, the required workforce and breadth of expertise also grow, making the system more difficult to design, manage, and operate.

Appropriate software support is essential for ensuring that hardware systems are easy to use, can be updated when necessary, and can operate in coordination with other embedded systems. Many applications can be implemented using inexpensive, application-specific hardware units. However, the lack of suitable software development environments often directs interest toward expensive, general-purpose solutions designed to support a wide range of applications.

The application scope of embedded systems can be expanded by providing suitable software support and developing efficient signal-processing and decision-making algorithms tailored to these systems. Increasing the number of embedded platforms on which researchers and users can easily develop applications enables many solutions to become more affordable, practical, and adaptable to changing requirements.

A complete embedded-system design process must address all hardware and software components. This requires the integration of hardware, software, and an appropriate software development environment to establish the foundation needed to implement the application selected for this project. The final requirement is the development of cost-effective application software. The proposed project is therefore interdisciplinary.

The project involves the design and implementation of a system-on-chip containing an application-specific instruction-set processor and its peripherals. The following stages will be carried out:

  1. Modeling and verifying the driver fatigue monitoring system.
  2. Implementing a RISC-V processor on an FPGA.
  3. Implementing the driver fatigue monitoring model on the FPGA-based RISC-V processor.
  4. Extending the RISC-V instruction set for driver fatigue monitoring and implementing the extended processor on an FPGA.
  5. Implementing and testing the driver fatigue monitoring model using the extended instruction set.
  6. Implementing the instruction-set-extended RISC-V processor as an ASIC.
  7. Implementing and testing the driver fatigue monitoring model on the RISC-V ASIC using the extended instruction set.

By following this methodology, the project aims to achieve Technology Readiness Level 5. An application area of particular importance to both Türkiye and Iran has been selected.

Every year, driver fatigue and loss of concentration cause numerous traffic accidents worldwide, resulting in fatalities, injuries, and financial losses. Traffic accident rates in Türkiye and Iran are higher than the global average.

The project will develop a driver-assistance solution that uses machine-learning and image-processing techniques to address two main objectives:

  1. Fatigue assessment.
  2. Concentration assessment.

The resulting solution will be a real-time, cost-effective embedded system designed to assist drivers.

Application-specific processor extensions will enable image-processing and machine-learning operations to be implemented in real time and at a lower cost. Designing both the hardware and software required for communication between the processor and its peripherals will also allow the system to operate with embedded-system components developed by different hardware manufacturers.

The project will improve the complete design process, covering low-level hardware, peripheral units, application software, and the end-user interface. Through this process, researchers will be able to design and implement systems containing specialized processors that satisfy the requirements of different applications.

The resulting system-on-chip will also be adaptable to other applications through software modifications. It will therefore be scalable and updatable through application-specific software development.

Project collaboration structure
RISC-V instruction-set extension

Methodology

The processing unit will be designed to access peripherals such as a DMA controller, a MIPI CSI-2 camera interface, and a USB data interface. To provide reliable communication between the processor and its peripherals, the processor must support standard interconnection protocols such as AXI4.

The AXI bus can support a wide range of peripheral units through APB bridges. The use of standard buses provides important advantages in terms of hardware availability, compatibility, and software-driver support.

The following fundamental components will first be designed and tested:

  • A software model of the driver fatigue detection system, including its image-processing and machine-learning algorithms.
  • A basic RISC-V processor implementation on an FPGA.
  • An instruction-set-extended RISC-V processor implementation on the development board.

Integration 1 — Initial Hardware Integration

Once the initial RISC-V implementation has been completed, integration of the processor with the camera and other hardware components on the development board can begin before the software model and instruction-set extensions are finalized.

This stage will enable issues related to the initial hardware integration to be identified and resolved. It is also required for collecting real-world data.

Integration 2 — Algorithm Integration with Real-World Data

Data collected using the hardware implementation will be used to train the driver fatigue detection model. The model will therefore be integrated with real-world data obtained from the project setup, allowing its accuracy and reliability to be evaluated under realistic conditions.

Integration 3 — Processor and Software-Model Integration

The final model parameters will be used to determine the required instruction-set extensions. Close cooperation between the algorithm-design and instruction-set-extension teams will therefore be necessary.

This stage will produce the first implementation of the driver fatigue detection algorithm on the RISC-V processor.

Integration 4 — Updated Software Model and Extended Processor

After the new instructions have been defined, the driver fatigue detection algorithm will be revised and rewritten to use these instructions. The compiler toolchain will also be tested during this integration stage.

The complete software flow, from the high-level algorithm and compiler to the generated machine code, will be evaluated.

Final Integration — Complete System

The machine code generated by the compiler will run on the instruction-set-extended RISC-V processor implemented on the FPGA of the development board. The processor will operate together with the cameras and other peripheral units to form the complete driver fatigue detection system.