Modeling and Implementation of Cybersecurity Protocols

Implementation and Acceleration of MLP-Based IDS for FPGA

  • Real-time implementation of neural networks for network security presents severe computational challenges on embedded systems.
  • To address this, a hardware/software (HW/SW) co-design approach is proposed to accelerate an Intrusion Detection System (IDS) utilizing a Multi-Layer Perceptron (MLP).
  • A custom accelerator for an FPGA platform is introduced, deployed alongside the open-source RV32IMF RISC-V processor, “Hornet”.
  • The accelerator design enables memory localization and parallelization of floating-point multiplications, thereby eliminating latency bottlenecks.
  • Results demonstrate a 63.8x speedup in single-input inference latency and a 97.1% reduction in energy consumption per inference compared to pure software execution.
  • The proposed HW/SW design maintains a robust overall accuracy of 78.86% and reduces BRAM utilization by 16.8%, offering a highly efficient deployment strategy for real-time cybersecurity acceleration.

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